//-----------------------Standard RISC-V defines, DO NOT TOUCH IT!-----------------
//---------------------------------RISCV opcode define-----------------------------
`define lui_encode 	                7'b0110111
`define auipc_encode	                7'b0010111
`define jal_encode	                7'b1101111
`define jalr_encode	                7'b1100111
`define branch_encode	            7'b1100011
`define load_encode 	                7'b0000011
`define store_encode	                7'b0100011
`define imm_encode	                7'b0010011
`define imm32_encode                 7'b0011011
`define reg_encode	                7'b0110011	                //R type指令opcode
`define reg32_encode                 7'b0111011	
`define mem_encode	                7'b0001111	                //MISC-MEM指令OPCODE，
`define system_encode                7'b1110011	
`define amo_encode	                7'b0101111
`define m32_encode	                7'b0111011

//------------------------------------RISC-V Privlage Defines---------------------
`define Machine                      2'b11
`define Supervisior                  2'b01
`define User                         2'b00
//------------------------------------CSRs----------------------------------------
//----------CSR index------------------------
//          User read only
`define uro_cycle_index 			    12'hc00	        //User read only, a shadow of Machine mode cycle counter
`define uro_time_index  			    12'hc01	        //User read only, a shadow of Machine mode time
`define uro_instret_index 		    12'hc02         //User read only, a shadow of instruction retired counter
`define uro_hpmcounter3_index		12'hc03         //User read only, performance counter3
`define uro_hpmcounter4_index 	    12'hc04         //User read only, performance counter4
`define urw_halt_index               12'hcc0         //halt pulse generate csr, write to this csr will cause a halt (for ysyx difftest use) 
`define urw_print_index              12'hcc1         //print function generate csr, value write to this csr will display on Simulation tool
//   Supervisior mode read and write
`define srw_sstatus_index			12'h100
`define srw_sie_index 			    12'h104
`define srw_stvec_index 			    12'h105
`define srw_scounteren_index 		12'h106
`define srw_sscratch_index 		    12'h140
`define srw_sepc_index 			    12'h141
`define srw_scause_index 			12'h142
`define srw_stval_index 			    12'h143
`define srw_sip_index 			    12'h144
`define srw_satp_index 			    12'h180
//    Machine mode read only
`define mro_mvendorid_index 		    12'hf11
`define mro_marchid_index 		    12'hf12
`define mro_mimp_index 			    12'hf13
`define mro_mhardid_index 		    12'hf14
`define mrw_mstatus_index 		    12'h300
`define mro_misa_index 			    12'h301
`define mrw_evangelion_index         12'hbc0         //Machine mode read/write, this csr is for sepecial use 
`define mrw_kernelcfg_index          12'hbc1         //Machine mode read/write, this csr is set to control some modules in kernel
//     Machine mode read and write
`define mrw_medeleg_index 		    12'h302
`define mrw_mideleg_index 		    12'h303	
`define mrw_mie_index 			    12'h304
`define mrw_mtvec_index 			    12'h305
`define mrw_mcounteren_index 		12'h306
`define mrw_mscratch_index 		    12'h340
`define mrw_mepc_index 			    12'h341
`define mrw_mcause_index 			12'h342
`define mrw_mtval_index 			    12'h343
`define mrw_mip_index 			    12'h344
`define mrw_pmpcfg0_index 		    12'h3a0
`define mrw_pmpaddr0_index 		    12'h3b0
`define mrw_pmpaddr1_index 		    12'h3b1
`define mrw_mcycle_index 			12'hb00
`define mrw_minstret_index 		    12'hb02
`define mrw_mhpcounter3_index 	    12'hb03
`define mrw_mhpcounter4_index	 	12'hb04
`define mrw_mcountinhibit_index      12'h320
`define mrw_mhpmevent3_index 		12'h323

//----------Async maskable interrupt---------
`define int_s_soft                   'd1             //s-mode software interrupt
`define int_m_soft                   'd3             //m-mode software interrupt
`define int_s_timer                  'd5
`define int_m_timer                  'd7
`define int_s_exter                  'd9
`define int_m_exter                  'd11
//-----------None maskable interrupt---------
`define nmi_PwrLost                  'd17            //power lost
`define nmi_EccErr                   'd18            //Ecc error
`define nmi_generic                  'd19            //NMI for general purpose use
//----------Sync exception-----------------
`define exc_InstrAddrMis             'd0
`define exc_InstrAccFlt              'd1
`define exc_illins                   'd2
`define exc_BreakPoint               'd3
`define exc_LoadAddrMis              'd4
`define exc_LoadAccFlt               'd5
`define exc_StoreAddrMis             'd6
`define exc_StoreAccFlt              'd7
`define exc_EcallFromU               'd8
`define exc_EcallFromS               'd9
`define exc_EcallFromM               'd11
`define exc_InstrPageFlt             'd12
`define exc_LoadPageFlt              'd13
`define exc_StorePageFlt             'd15
//---------------------------------Sv39CT defines-----------------------------------
`define Sv39_V 			            0
`define Sv39_R			            1
`define Sv39_W			            2
`define Sv39_X			            3
`define Sv39_U			            4
`define Sv39_G			            5
`define Sv39_A			            6
`define Sv39_D 			            7
`define Sv39_C			            63                          //can be cache
`define Sv39_T			            62                          //write Through
`define Sv39_Bare                    4'h0
`define Sv39_On                      4'h8
//-----------------------------------TLB & MMU modules commands----------------------------
`define TLB_CMD_NOP                  8'h00
`define TLB_CMD_rLUT                 8'h01
`define TLB_CMD_wLUT                 8'h02
`define TLB_CMD_xLUT                 8'h03
`define TLB_CMD_FLUSH                8'h05
`define TLB_RPL_NOP                  8'h00
`define TLB_RPL_rPERR                8'h11                   //读页面错误
`define TLB_RPL_wPERR                8'h12                   //写页面错误
`define TLB_RPL_xPERR                8'h13                   //执行页面错误
`define TLB_PRL_RDY                  8'h80
//--------------------------------FIB bus commands-----------------------------------------
`define FIB_CMD_NOOP                 8'h00
`define FIB_CMD_SIGR                 8'h01
`define FIB_CMD_SIGW                 8'h02
`define FIB_CMD_SEQR                 8'h03
`define FIB_CMD_SEQW                 8'h04
`define FIB_CMD_WAPR                 8'h05
`define FIB_CMD_WAPW                 8'h06
`define FIB_CMD_AMOR                 8'h07
`define FIB_CMD_AMOW                 8'h08
`define FIB_CMD_SEQE                 8'h14
//                        FIB-A extension
`define FIB_CMD_LR                   8'h20
`define FIB_CMD_SC                   8'h21
`define FIB_CMD_AMOSWAP              8'h22
`define FIB_CMD_AMOADD               8'h23
`define FIB_CMD_AMOXOR               8'h24 
`define FIB_CMD_AMOAND               8'h25
`define FIB_CMD_AMOOR                8'h26
`define FIB_CMD_MIN                  8'h27
`define FIB_CMD_MAX                  8'h28
`define FIB_CMD_MINU                 8'h29
`define FIB_CMD_MAXU                 8'h2A
//                         FIB reply
`define FIB_RPL_NOOP                 8'h00
`define FIB_RPL_TRDY                 8'h10                   //Transmission Ready
`define FIB_RPL_SEQ                  8'h14
`define FIB_RPL_MODF                 8'h20                   //Modify Data (if have)
`define FIB_RPL_TERR                 8'hF0
`define FIB_RPL_IDLE                 8'hFF
//----------------------------------IDU instructions---------------------------------------

//-----------------------------------ALU operation defines---------------------------------
`define ALU_NOP         8'h00                       //No operation, nothing happen
`define ALU_JAL         8'h03                       //rd_data <= pc+4
`define ALU_CSRW        8'h04                       //if(ds1==ds2) BPflt <= 0; else BPflt <= 1
`define ALU_CSRS        8'h05
`define ALU_CSRC        8'h06
`define ALU_ADD         8'h08
`define ALU_SUB         8'h0F
`define ALU_SLT         8'h09
`define ALU_XOR         8'h0A
`define ALU_OR          8'h0B
`define ALU_AND         8'h0C
`define ALU_SL          8'h0D
`define ALU_SR          8'h0E
//       some shits
`define ALU_BCDADD      8'h10
`define ALU_BCDMIN      8'h11
`define ALU_BCDADJ      8'h12
`define ALU_BCDIADJ     8'h13
//--------------------------------LSU operation defines-------------------------------------
//-------------------------------
`define LSU_NOP         8'h00
`define LSU_eXecute     8'h01   //Abandoned
`define LSU_READ        8'h02
`define LSU_WRITE       8'h03
`define LSU_TLBRef      8'h06                       //TLB entry refersh
`define LSU_CacheRef    8'h07                       //Cache refersh (write back all modification and disvalid)
//RV-A
`define LSU_READ_Lock   8'h20   //Abandoned                    //Read from memory, and Lock the bus LR
`define LSU_WRITE_Unloc 8'h21   //Abandoned                    //Write to memory, and release bus  SC
`define LSU_AMOSWAP     8'h22
`define LSU_AMOADD      8'h23
`define LSU_AMOXOR      8'h24
`define LSU_AMOAND      8'h25
`define LSU_AMOOR       8'h26
`define LSU_AMOMAX      8'h27
`define LSU_AMOMIN      8'h28
`define LSU_AMOMAXU     8'h29
`define LSU_AMOMINU     8'h2A
//--------------------------------Mcop operation defines-----------------------------------
`define Mcop_NOP        8'h00
`define Mcop_MUL        8'h01
`define Mcop_MULH       8'h02
`define Mcop_MULHS      8'h03
`define Mcop_DIV        8'h04
`define Mcop_REM        8'h05
//--------------------------------Operation Information Defines----------------------------
`define Sign64          2'b00                       //Sign extension, 64bit operation
`define Sign32          2'b10                       //Sign extension, 32bit operation
`define Unsign64        2'b01                       //Unsign ............
`define Unsign32        2'b11                       //Unsign ............
`timescale 1ns/100ps